Network Processors

It is not a detailed description of how a Network Processor works. Just trying to differentiate Network processor from other common chip solutions.

For networks to effectively handle new applications emerging in the market, they will need to support new protocols that include differentiated services, security, and various network management functions. While networks are demanding equipment with very high throughput, they also need the flexibility to support new protocols and applications. In addition, the ever-changing requirements of network equipment require solutions that can be brought to market quickly.

Today’s legacy network implementations are based on Field Programmable Gate Arrays (FPGAs) for lower layer processing and General Purpose Processors (GPPs) for higher layer processing. Neither of these solutions meets all the requirements that network processing demands. Consider the broad categories of alternatives for system implementation:

ASIC (Application Specific Integrated Circuit) – any hardwired solution.

ASIP (Application Specific Instruction Processor) – an instruction set processor specialized for a particular application domain.

Co-processor – a hardwired, possibly configurable solution with a limited programming interface.

FPGA (Field Programmable Gate Array) – a device that can be reprogrammed at the gate level.

GPP (General Purpose Processor) – a programmable processor for general purpose computing.

There are two main requirements for all these solutions - flexibility and performance. ASICs are the most hardwired (least flexible), but provide the highest performance. GPPs are the most general (flexible) at the cost of the lowest performance. An ASIP for networking provides the right balance of hardware and software to meet all the requirements like:

Performance – by executing key computational kernels in hardware, NPs are able to perform many applications at wire speed.

Flexibility – having software as a major part of the system allows network equipment to easily adapt to changing standards and applications.

Fast TTM – designing software is much faster (and cheaper) than designing hardware of equivalent functionality.

A network processor is an ASIP for the networking application domain – a software programmable device with architectural features and/or special circuitry for packet processing. Main players in the NP market space are AMCC, Agere, Intel, Broadcom, Cisco and Vitesse.

A very detailed analysis of NPs is available in Understanding NPs. Another good article on NPs is from Netrino.

FPGAs Vs ASICs

Basically Field Programmable Gate Arrays(FPGAs) and Application Specific ICs(ASICs) are Programmable Logic Devices(PLDs). Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons.A comparison of the advanatages and disadvantages of both of them are given below.

FPGA Design Advanatages

• Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and developer can directly burn the HDL code.
  

• No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. Sometimes its free. ASIC youpay huge NRE and tools are expensive.
  

• Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.

• More predictable project cycle: The FPGA design flow eliminates potential re-spins of the project since the design logic is already synthesized and verified in FPGA device.

• Field Reprogramability: A new program can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take a huge amount of money and time to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.

• Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. If design has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.

• FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC.

• Generally FPGAs are used for lower speed, lower complexity and lower volume designs. But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.

• Unlike ASICs, FPGA's have special hardwares such as Multiply and Accumulator modules (MACs) , memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera are examples. There are FPGAs available now with built in ADC. Using all these features designers can build a system on a chip.
  

FPGA Design Disadvanatges

• Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race.
  

• You have to use the resources available in the FPGA. Thus FPGA limits the design size.

• Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.

ASIC Design Advantages

• Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.

• ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.

• Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life.
  

• In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.

• In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out.

ASIC Design Disadvantages

• Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.

• Design Issues: Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA is an IC and designed by ASIC design enginner !!)

• Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.

A good article (more technical one) comparing each factors determining the selection fo ASICs and FPGAs is available here:

http://www.soccentral.com/results.asp?CategoryID=488&EntryID=15887

Note: Analysis , Synthesis, floorplanning, place and route, timing analysis and verification are some of the steps in the design flow of ICs. Will explain about these steps in some other post.

Hardware Description languages

Hardware description languages (HDL) are languages used for the formal description of a hardware behaviour. When we have a lot of software programming languages like C, C++ which are well used in
embedded world, why we need HDLs? The basic reason is software programming languages are not well tuned or designed for implementing two basic attributes of hardware : Time and Concurrency.

In Software, processes are generally described to be executed serially. But in hardware concurrent processes are important and succesfull working of hardware depends on the proper execution during specified clock cycles. Ofcourse, these can be implemented in traditional programming languages like C++, but it is not effective compared to HDLs.

Mainly, HDLs have two purposes:

1. To make a prototype. Means, to write a model for the expected behaviour of the circuit, before the actual circuit is designed and built. In this case, the HDL program is given as input to a Simulator.

2. To make actual hardware. In this case, HDL is used to make detailed description of the hardware and it is given as input to a logic compiler. The output of compiler is used to program a programmable logic device.

How HDL compiler works? HDL compiler works in several stages. First it will generate the logic description file in proprietary format of the chip vendor. For eg : ALTERA, XILINX. Then it is converted to a industry standard format like EDIF( Elctronic Design Interchange Format). Then it is converted to a JEDEC format file. JEDEC format file contains the instructions for a PLD programmer to write the logic to the PLDs like FPGAs and ASICs.

Commonly used HDLs include

1. VHDL( Very High Speed IC Hardware Description Language)
2. Verilog

Some propreitary HDLs like Altera HDL (AHDL) are also available.